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? semiconductor components industries, llc, 2006 october, 2006 - rev. 2 1 publication order number: TY72011AP2/d customer specific device from on semiconductor advance information single ended pwm controller featuring qr operation and soft frequency foldback the TY72011AP2 combines a true current mode control modulator and a demagnetization detector to ensure full discontinuous conduction mode in any load/line conditions and minimum drain voltage switching (quasi-resonant operation). thanks to its inherent v ariable frequency mode (vfm), the controller decreases its operating frequency at constant peak current whenever the output power demand diminishes. associated with automatic multiple valley switching, this unique architecture guarantees minimum switching losses and the lowest power drawn from the mains when operating at no-load conditions. the internal high-voltage current source provides a reliable charging path for the vcc capacitor and ensures a clean and short start-up sequence without deteriorating the efficiency once off. finally, the continuous feedback signal monitoring implemented with an over-current fault protection circuitry (ocp) makes the final design rugged and reliable. an internal over v oltage protection (ovp) circuit continuously monitors the vcc pin and stops the ic whenever its level exceeds 40 v. the internal ovp connection is also externally available to precisely adjust the final protection level to the designer needs. device package shipping ordering information typ2011ap2 pdip-14 25 units/rail typ2011ap2g pdip-14 (pb-free) 25 units/rail features ? natural drain-source valley switching for lower emi and quasi-resonant operation ? current mode control ? smooth frequency foldback for low standby power and minimum output ripple at no-load ? internal 200 ns leading edge blanking on current sense ? wide uvlo levels: 9.3 to 15 v typical ? 250 ma sink and source driver ? wide operating voltages: 8.0 to 36 v with fixed over voltage protection (ovp) on the v cc or adjustable through a dedicated pin ? internal short-circuit protection ? integrated 3.0 ma typ. start-up source applications ? off-line charger ? standby smps ? wall adapters ? power supplies for: dvd players set-top boxes, etc. pdip-14 p suffix case 646 pin connections 14 1 hv 14 v cc 2 demag 3 fb 4 ct 13 drive 12 isense 11 gnd marking diagram a = assembly location wl = wafer lot yy = year ww = work week g = pb-free package 1 1 14 5 6 7 10 9 8 nc ovp nc nc nc nc TY72011AP2 awlyywwg this document contains information on a new product. specifications and information herein are subject to change without notice. TY72011AP2 free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 2 figure 1. a typical off-line adapter application TY72011AP2 + + + + 4x1n4007 c1 10 f 400 v r8 22 k r6 2.7 k r1 560 universal input r2 15 c14 33 f/35 v d2 1n4148 d6 1n5819 l2 10 h c11 47 f 10 v ic4 sfh6156-2 c12 1 nf c10 470 f 10 v 5 v m2 mtd1n60e r4 6.8 d7 4.3 v 1 14 2 3 4 13 12 11 5 6 7 10 9 8 rovpl rovpu r5 15 r3 3.3 pin function description pin number pin name function description 1 hv start-up rail connected to the rectified hv rail, this pin provides a charging path to v cc bulk capacitor. 2 nc - - 3 demag zero primary-current detection this pin ensures the re-start of the main switcher when operating in free-run. 4 fb feedback signal to control the pwm this level modulates the peak current level in free-running operation and modulates the frequency in vfm operation. 5 ct timing capacitor by adding a capacitor from ct to the ground, the user selects the minimum operating frequency. 6 ovp overvoltage pin by applying a level of 2.8 v typical on this pin, the ic is permanently latched-off until v cc falls below uvlo l . 7 nc - - 8 nc - - 9 nc - - 10 gnd the ic's ground - 11 isense the primary-current sensing pin this pin senses the primary current via an external shunt resistor. 12 drv this pin drives the external switcher the ic is able to deliver or absorb 250 ma peak currents while delivering a clamped driving signal. 13 v cc powers the ic a positive voltage up to 40 v typical can be applied upon this pin before the ic stops. 14 nc - - free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 3 figure 2. simplified block diagram 3 4 - + - + - + internal regulator internal clamp demag ? last pulse of demag after 4 s flip-flop over voltage protection (v cc > 40 v) lasts more than 128 ms? --> protection circuitry v co feedback t off = f (v err ) max t off = f (ct) over current protection (ocp) v(-) < 1.5 v v err max = 3 v v err min = 10 mv internal v cc ri rf 1 5 200 ns l.e.b 2.5 v 1/3 - + 14 clock rq d driver current comparator 250 mv - 1 v max setpoint hv demag fb ct v cc drv i sense gnd startup uvlo h = 15 v uvlo l = 9.3 v 250 mv clamp 1 v v err 2 7 6 13 12 11 10 8 9 20 k ovp - + - + ovp 60 mv 500 4 x 10 v zener v cc pin 8 v cc pin 13 nc nc ovp nc nc free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 4 maximum ratings rating pin # symbol value unit min max power supply voltage 8 v in - 45 v thermal resistance junction-to-air - r ja - 100 c/w operating ambient temperature maximum junction temperature - t a t jmax - -25 to +85 150 c c storage temperature range - t stg - -60 to +150 c esd capability, hbm model all pins - - 2.0 kv esd capability, machine model all pins - - 200 v demagnetization pin current 3 - - 5.0 ma electrical characteristics (for typical values t a = 25 c, for min/max values t a = -25 c to +85 c, max t j = 150 c, v cc = 12 v unless otherwise noted.) characteristics pin # symbol min typ max unit demagnetization block input threshold voltage (v pin2 increasing) 3 vth 50 65 85 mv hysteresis (v pin2 decreasing) 3 v h - 30 - mv input clamp voltage high state (i pin2 = 3.0 ma) low state (i pin2 = -3.0 ma) 3 vc h vc l 8.0 -0.9 10 -0.7 12 -0.5 v demag propagation delay - - 100 300 350 ns no demag signal activation - - - 4.0 8.0 s internal input capacitance at 1.0 v 3 c pin3 - 10 - pf demag propagation delay with 22 k external resistor 3 - 100 370 480 ns feedback path (for typical values t a = 25 c, for min/max values t a = -25 c to +85 c, max t j = 125 c unless otherwise noted.) input impedance at v fb = 3.0 v 4 zin - 50 - k internal error amplifier closed loop gain 4 av cl - -3.0 - - internal built-in offset voltage for error detection - vref 2.2 2.5 2.8 v error amplifier level of vco take over - - - 1.0 - v internal divider from internal error amp, pin to current setpoint - - - 3.0 - - fault detection circuitry internal over current level - wl l - 1.5 - v fault time duration to latch activation @ ct = 1.0 f - - - 128 - ms over current latch-off phase @ ct = 1.0 f - - - 1.02 - s hysteresis when v fb goes back into regulation - - - 100 - mv v cc (pin 13) over voltage protection 13 ovp1 36 40 43 v over voltage protection 6 ovp2 2.5 2.8 3.1 v current comparator input bias current @ 1.0 v 11 i ib - 0.02 - a maximum current setpoint 11 vcl 0.9 1.0 1.1 v minimum current setpoint 11 v min 225 250 285 mv free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 5 electrical characteristics (continued) (for typical values t a = 25 c, for min/max values t a = -25 c to +85 c, max t j = 150 c, v cc = 12 v unless otherwise noted.) characteristics pin # symbol min typ max unit current comparator (continued) propagation delay from current detection to gate off state 11 tdel - 200 250 ns leading edge blanking (leb) 11 tleb - 200 - ns variable frequency modulator minimum frequency operation @ ct = 1.0 f and v cc = 35 v 5 fmin - 0 - khz maximum frequency operation @ ct = 1.0 f and v cc = 35 v 5 fmax 90 110 125 khz minimum ct charging current (note 1) 5 i ct min - 0 - a maximum ct charging current (note 1) 5 i ct max 280 350 420 a discharge time @ ct = 1.0 f 5 - - 500 - ns drive output output voltage rise time @ c l = 1.0 f ( v = 10 v) 12 tr - 60 100 ns output voltage fall time @ c l = 1.0 f ( v = 10 v) 12 tf - 40 100 ns clamped output voltage @ v cc = 35 v (note 2) 12 v drv 11 13 16 v voltage drop on the stage @ v cc = 10 v (note 2) 12 v drv - - 0.5 v undervoltage lockout startup threshold (v cc increasing) 13 uvlo h 13.5 15 16.5 v minimum operating voltage (v cc decreasing) 13 uvlo l 8.3 9.3 10.0 v internal startup current source maximum voltage, pin 1 grounded 1 - - 450 - v maximum voltage, pin 1 decoupled (470 f) 1 - - 500 - v startup current flowing through pin 1 1 - 2.5 3.0 4.5 ma leakage current in offstate @ vpin 1 = 500 v 1 - - 32 70 a device current consumption v cc less than uvlo h 13 - - 1.5 1.8 ma v cc = 35 v and fsw = 2.0 khz, c l = 1.0 f 13 - - 1.2 3.0 ma v cc = 35 v and fsw = 125 khz, c l = 1.0 f 13 - - 3.0 4.0 ma startup current to v cc capacitor 13 - 1.5 - - ma 1. typical capacitor swing is between 0.5 v and 3.5 v. 2. guaranteed by design, t j = 25 c. free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 6 theory of operation introduction by implementing a unique smooth frequency reduction technique, the ty72011 represents a major leap toward low-power switch-mode power supply (smps) integrated management. the circuit combines free-running operation with minimum drain-source switching (so-called valley switching), which naturally reduces the peak current stress as well as the electromagnetic interferences (emi). at nominal output power, the circuit implements a traditional current-mode smps whose peak current setpoint is given by the feedback signal. however, rather than keeping the switching frequency constant, each cycle is initiated by the end of the primary demagnetization. the system therefore operates at the boundary between discontinuous conduction mode (dcm) and continuous conduction mode (ccm). figure 3 details this terminology: figure 3. 0 0 dead-time time 0 before turn on not 0 at turn on on off d/fs i l(avg) i l i p l < lc l > lc l = lc borderline ccm dcm when the output power demands decreases, the natural switching frequency raises. as a natural result, switching losses also increase and degrade the smps efficiency. to overcome this problem, the maximum switching frequency of the ty72011 is clamped to typically 125 khz. when the free running mode (also called borderline control mode, bcm) reaches this clamp value, an internal voltage-controlled oscillator (vco) takes over and starts to decrease the switching frequency: we are in variable frequency mode (vfm). please note that during this transition phase, the peak current is not fixed but is still decreasing because the output power demand does. at a given state, the peak current reaches a minimum height (typically 250 mv/rsense), and cannot go further down: the switching frequency continues its decrease down to a possible minimum of 0 hz (the ic simply stops switching). during normal free-running operation and vfm, the controller always ensures single or multiple drain-source valley switching. we will see later on how this is internally implemented. the flyback operation is mainly defined through a simple formula: pout 1 2 lpip 2 fsw (eq.1) with: lp the primary transformer inductance (also called the magnetizing inductance) ip the peak current at which the mosfet is turned off fsw the nominal switching frequency to adjust the transmitted power, the pwm controller can play on the switching frequency or the peak current setpoint. to refine the control, the ty72011 offers the ability to play on both parameters either altogether or on an individual basis. free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 7 in order to clarify the device behavior, we can distinguish the following simplified operating phases: 1. the load is at its nominal value. the smps operates in borderline conduction mode and the switching frequency is imposed by the external elements (vin, lp, ip, vout). the mosfet is turned on at the minimum drain-source level. 2. the load starts to decrease and the free-running frequency hits the internal clamp. 3. the frequency can no longer naturally increase because of the clamp. the frequency is now controlled by the internal vco but remains constant. the peak current finds no other option that diminishing to satisfy equation (1). 4. the peak current has reached the internal minimum ceiling level and is now frozen for the remaining cycles. 5. to further reduce the transmitted power (v fb goes up), the vco decreases the swit ching frequency. in case of output overshoot, the vco could decrease the frequency down to zero. when the overshoot has gone, v fb diminishes again and the ic smoothly resumes its operation. advantages of the method by implementing the aforementioned control scheme, the ty72011 brings the following advantages: ? discontinuous only operation: in dcm, the flyback is a first order system (at low frequencies) and thus naturally eases the feedback loop compensation. ? a low-cost secondary rectifier can be used thanks to smooth turn-off conditions. ? valley switching ensures minimum switching losses brought by coss and all the parasitic capacitances. ? by folding back the switching frequency, you turn the system into pulse duration modulation. this method prevents from generating uncontrolled output ripple as with hysteretic controllers. ? by letting you control the peak current value at which the frequency goes down, you ensure that this level is low enough to avoid transformer acoustic noise generation even at audible frequencies. detailed description the following sections describe the internal behavior of the ty72011. free-running operation as previously said, the operating frequency at nominal load is dictated by the external elements. we can split the different switching sections in two separated instants. in the following text we use the internal error voltage, verr. this level is elaborated as figure 7 portrays. verr is linked to vfb (pin 4) by the following formula: verr 10 3v fb on time: the on time is given by the time it takes to reach the peak current setpoint imposed by the level on fb pin (pin 4). since this level is internally divided by three, the peak setpoint is simply: ipk 1 3rsense verr (eq.2) the rising slope of the peak current is also dependent on the inductance value and the rectified dc input voltage by: dil dt vin dc lp (eq.3) by combining both equations, we obtain the on time definition: ton lp vin dc ip lpv err vin dc 3rsense (eq.4) off time: the time taken by the demagnetization of the transformer depends on the reset voltage applied at the switch opening. during the conduction time of the secondary diode, the primary side of the transformer undergoes a reflected voltage of: [np/ns . (vf + vout)]. this voltage applied on the primary inductance dictates the time needed to decrease from ip down to zero: toff lp np ns (vout vf) (eq.5) ip lpverr np ns (vout vf) 3rsense by adding ton + toff, we obtain the natural switching frequency of the smps operating in borderline conduction mode (bcm): (eq.6) ton toff verrlp 3rsense 1 vin dc 1 np ns (vout vf)
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TY72011AP2 http://onsemi.com 8 if we now enter this formula into a spreadsheet, we can easily plot the switching frequency versus the output power demand: figure 4. free running frequency vs. output power 150000 0 250000 50000 100000 200000 015 10 5 switching frequency (hz) transition bcm to vfm output power (w) 20 fmax fmax v co action the typical above diagram shows how the frequency moves with the output power demand. the components used for the simulation were: vin = 300 v, lp = 6.5 mh, vout = 10 v, np/ns = 12. the red line indicates where the maximum frequency is clamped. at this time, the vco takes over and decreases the switching frequency to the minimum value. vco operation the vco is controlled from the verr voltage. for verr levels above 1.0 v, the vco frequency remains unchanged at 125 khz. as soon as verr starts to decrease below 1.0 v, the vco frequency decreases with a typical small-signal slope of -175 khz/mv @ verr = 500 mv down to zero (typically at fb 3.3 v). the demagnetization synchronization is however kept when the toff expands. the maximum switching frequency can be altered by adjusting the ct capacitor on pin 5. the 125 khz maximum operation ensures that the fundamental component stays external from the international emi cispr-22 specification beginning. the following drawing explains the philosophy behind the idea: figure 5. 3 v 1 v 0.75 v peak current is fixed bcm mode peak current can change v co frequency is fixed at 130 khz v co frequency can decrease internal v err free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 9 figure 6. 2 750.0 u 754.0 u 758.0 u 762.0 u 766.0 u i p = 0 auxiliary level restart when demag is too low 65 mv 0 v valley switching drain level possible demag 4 s zero crossing detector to detect the zero primary current, we make use of an auxiliary wi nding. by coupling this winding to the primary, we have a voltage image of the flux activity in the core. figure 6 details the shape of the signal in bcm. the auxiliary winding for demagnetization needs to be wired in forward mode only. as figure 6 depicts, when the mosfet closes, the auxiliary winding delivers (naux/np . vin). at the switch opening, we couple the auxiliary winding to the main output power winding and thus deliver: (-naux/ns . vout). when dcm occurs, the ringing also t akes place on the auxiliary winding. as soon as the level crosses-up the internal reference level (65 mv), a signal is internally sent to re-start the mosfet. three different conditions can occur: 1. in bcm, every time the 65 mv line is crossed, the switch is immediately turned-on. by accounting for the internal demag pin capacitance (10-15 pf typical), you can introduce a fixed delay, which, combined to the propagation delay, allows to precisely re-start in the drain-source valley (minimum voltage to reduce capacitive losses). 2. when the ic enters vfm, the vco delivers a pulse which is internally latched. as soon as the demagnetization pulse appears, the logic re-starts the mosfet. 3. as can be seen from figure 6, the p arasitic oscillations on the drain are subject to a natural damping, mainly imputed to ohmic losses. at a given point, the demag activity on the auxiliary winding becomes too low to be detected. to avoid any re-start problem, the ty72011 features an internal 4.0 s timeout delay. this timeout runs after each demag pulse. if within 4.0 s further to a demag pulse no activity is detected, an internal signal is combined with the vco to actually re-start the mosfet (synchronized with ct). free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 10 error amplifier and fault detection the ty72011 features an internal error amplifier solely used to detect an overcurrent problem. the application assumes that all the error gain associated with the precise reference l evel is located on the secondary side of the smps. various solutions can be purposely implemented such as the tl431 or a dedicated circuit like the mc33341. in the ty72011, the internal opamp is used to create a virtual ground permanently biased at 2.5 v (figure 7), an internal reference level. by monitoring this virtual ground further called v(-), we have the possibility to confirm the good behavior of the loop. if by any mean the loop is broken (shorted optocoupler, open led etc.) or the regulation cannot be reached (true output short-circuit), the opamp network is adjusted in order to no longer be able to ensure the 2.5 v virtual point v(-). if v(-) passes down the 1.5 v level (e.g. output shorted) for a time longer than 128 ms, then the pulses are stopped for 8 x 128 ms. the ic enters a kind of burst mode with bunch of pulses lasting 128 ms and repeating every 8 x 128 ms. if the loop is restored within the 8 x 128 ms period, then the pulses are back again on the output drive (synchronized with uvlo h ). figure 7. - + v(-) ri 50 k - + + + + 2r r ocp circuitry current setpoint v fb v low 1.5 v v fb v1 2.5 v v high = 3 v v low = 5 mv 1 2 3 5 6 7 rf 150 k monitor to illustrate how the system reacts to a variable fb level, we have entered the above circuit into a spice simulator and observed the output waveforms. when fb is within regulation, the error flag is low. however, as soon as fb leaves its normal operating area, the opamp can no longer keep the v(-) point and either goes to the positive top or down to zero: the error flag goes high. because of the large amount of delay necessary for this 128 ms operation, the capacitor used for the timing is ct, connected from ground to pin 5. in normal vfm operation, this timing capacitor serves as the vco capacitor and the error management circuit is transparent. as soon as an error is detected (error flag goes high), an internal switch routes ct to the 128 ms generator. as a first effect, the switching frequency is no longer controlled by the vco (if the error appears during vfm) and the system is relaxed to natural bcm. the capacitor now ramps up and down to be further divided and finally create the 128 ms delay. free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 11 figure 8. regulation area ocp condition error flag virtual point fb 1.5 v 1.000 m 3.000 m 5.000 m 7.000 m 9.000 m 6.500 4.500 2.500 500.0 m as soon as the system recovers from the error, e.g. fb is back within its regulation area, the ic operation comes back to normal. to avoid any system thermal runaway, another internal 8 x 128 ms delay is combined with the previous 128 ms. it works as follow: the 128 ms delay is provided to account for any normal transients that engender a temporary loss of feedback (fb goes toward ground). however, when the 128 ms period is actually over (the feedback is definitively lost) the ic stops the output driving pulses for a typical period of 8 x 128 ms. during this mode, the rest of the functions are still activated. for instance, in lack of pulses, the self-supplied being no longer provided, the start-up source turns on and off (when reaching the corresponding uvlo l and uvlo h levels), creating an hiccup waveform on the vcc line. as soon as the feedback condition is restored, the 8 x 128 ms is interrupted and, in synchronism with the vcc line, the ic is back to normal. the following diagrams show how this mechanism takes place when fb is down to zero (optocoupler opened) or up to vcc (optocoupler shorted). if we assume that the error is permanently present, then a burst mode takes place with a 128/8 x 128 = 12.5% duty-cycle. the real transmitted power is thus: pout burst 1 2 lpip 2 fswduty burst over voltage conditions (ovp) are detected by monitoring the vcc level. as figure 9 describes, three 10 v zener plus one 5.0 v zener are connected in series together with a 18 k to ground. as soon as vcc exceeds 40 v typical , a current starts to flow in the 18 k resistor. when the voltage developed across this element exceeds 2.5 v, an error is triggered and immediately latches the ic off. in lack of switching pulses, the vcc capacitor is no longer refreshed by the auxiliary supply and slowly discharges toward ground. w hen the vcc level crosses uvlo l , a new startup sequence occurs. if the ovp has gone, normal ic operation takes place. for different ovp levels, the comparator input is accessible through pin 6. figure 9. - + + 2.5 v latched ovp 5 v 10 v 18 k 10 v 10 v 6 5 4 3 2 1 7 v cc 8 2 k ovp free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 12 v cc drive unit v cc reaches uvlo l ovp uvlo h uvlo l 40 v 8 x 128 ms maximum if loop does not recover uvlo h uvlo l 3.5 v loop recovers here 1.5 v v cc drive v(-) 128 ms arbitrary v cc representation figure 10. over voltage protection diagram figure 11. v(-) level passes under 1.5 v free datasheet http://www.datasheet-pdf.com/
TY72011AP2 http://onsemi.com 13 package dimensions pdip-14 case 646-06 issue p 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n -t- 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 TY72011AP2/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative free datasheet http://www.datasheet-pdf.com/

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